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MOUNTAIN VIEW, Calif.----Nov. 6, 2000-- Synopsys Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced the release of FPGA Compiler II(TM) and FPGA Express(TM) version 3.5. With this latest release, Synopsys introduces significant enhancements that increase designers' productivity and enable new high-end synthesis design flows, including support for Altera's IP encryption and Altera's Excalibur(TM) system-on-a-programmable-chip (SOPC). Considerable runtime reductions and dramatic quality of results (QoR) improvements make version 3.5 Synopsys' most extensive FPGA synthesis release to date.

First to Integrate Altera IP Encryption

Working jointly with Altera, Synopsys created the first and only solution that embeds the Altera IP encryption algorithms within commercial FPGA design products. ``The inclusion of the Altera IP encryption flow within FPGA Compiler II and FPGA Express opens the door to significant new system-on-a-programmable-chip solutions for programmable logic designers using a synthesis flow. Designers can now easily and seamlessly incorporate the newest advanced IP MegaCore® functions from Altera or third party IP from Altera Megafunction Partners Program (AMPP(SM)) members,'' said David Greenfield, Altera director of development tools marketing.

Significant Reduction in Runtime

Using the normal default settings, runtime reductions of 25% or more are standard in the latest release of FPGA Compiler II and FPGA Express. To further reduce design runtime, Synopsys has also added a new ``Fast'' compile option. An additional runtime reduction of up to 20% is achievable using the new ``Fast'' option.

Enabling Altera's Excalibur Embedded Processors

Combining logic, memory, and processor cores, Altera's Excalibur embedded System-on-a-Programmable-Chip (SOPC) solutions allow designers the flexibility to embed processor cores with flexible programmable logic. FPGA Compiler II and FPGA Express version 3.5 are integrated with Altera's high-density SOPC design flow and enable designers working on next generation networking and communications equipment to realize their time-to-market goals. Because of Synopsys' experience with advanced synthesis technologies, FPGA Compiler II and FPGA Express are the synthesis tools of choice for designers using Altera's Excalibur embedded processor devices.

New Easy-to-Use DesignWizard Graphical Entry

Synopsys introduces the DesignWizard graphical flow, which increases productivity by automatically guiding users through the complete synthesis process. Designers new to synthesis or without formal training on FPGA synthesis tools can easily complete an entire chip using this simple graphical flow, thus increasing design team productivity and dramatically cutting design time.

Enhanced Architecture Optimizations Deliver Top Quality of Results

In version 3.5, Synopsys' commitment to FPGA synthesis is further demonstrated by its engineering investment in quality of results (QoR). Constraints can now be imported and exported using an ASCII format complementing FPGA Compiler II's constraint-driven synthesis. This greatly reduces design time and accelerates design flexibility when doing ``what if'' constraint-driven synthesis scenarios.

Synopsys' Block-Level Incremental Synthesis (BLIS) now exports multiple timing constraint files for Xilinx Virtex devices. This enhancement to BLIS further reduces time spent on re-synthesis iterations and on lengthy place-and-route iterations for multimillion-gate devices, while automatically recalculating timing across the entire design, taking into account the unmodified portions.

Support of automatic ROM inference, which significantly improves QoR, is expanded to include Actel 54SX, Altera APEX20K, and Xilinx Virtex-II. ROMs are automatically recognized and mapped to architecture-specific primitives.

FPGA Compiler II and FPGA Express add Synopsys' industry-standard STAMP(TM) timing model support of IP for the Lucent ORCA3(TM) FPSC family. Using STAMP timing models leads to the greatest optimization of primary inputs/outputs and the effective use of synthesis constraints when designing with IP.

New Device Support

Synopsys continues to be the first to bring designers the most up-to-date support for all leading FPGAs and CPLDs. The following new device support has been added to both FPGA Compiler II and FPGA Express version 3.5:

                           Actel eX Family

                           Altera MAX 7000B

                         Lattice ispMACH4000

                            LightSpeed 4E

                             Lucent ORCA4

                             Triscend A7

                    Xilinx Virtex-II and Virtex-EM

Availability

FPGA Compiler II and FPGA Express version 3.5, as well as additional information about the industry-leading Synopsys FPGA synthesis product line, are available now at http://www.synopsys.com/FPGA.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Note to Editors: Synopsys is a registered trademark, FPGA Compiler II, FPGA Express, and STAMP are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

     Synopsys, Inc.
     Heather Kettmann, 650/584-4723
     kettmann@synopsys.com
        or
     KVO Public Relations
     Sonia Harrison, 503/221-2369
     sonia_harrison@kvo.com